The development of semiconductor switching technology for high power applications in motor drive circuits, appliance controls and lighting ballasts, for example, began with the bipolar junction transistor. As the technology matured, bipolar devices became capable of handling large current densities in the range of 40-50 A/cm.sup.2, with blocking voltages of 600 V.
Despite the attractive power ratings achieved by bipolar transistors, there exist several fundamental drawbacks to the suitability of bipolar transistors for all high power applications. First of all, bipolar transistors are current controlled devices. For example, a large control current into the base, typically one fifth to one tenth of the collector current, is required to maintain the device in an operating mode. Even larger base currents, however, are required for high speed forced turn-off. These characteristics make the base drive circuitry complex and expensive. The bipolar transistor is also vulnerable to failure if a high current and high voltage are simultaneously applied to the device, as commonly required in inductive power circuit applications, for example. Furthermore, it may be difficult to parallel connect these devices since current diversion to a single device may occur, making emitter ballasting schemes necessary.
The power MOSFET was developed to address this base drive problem. In a power MOSFET, a gate electrode bias is applied for turn-on and turn-off control. Turn-on occurs when a conductive inversion-layer channel is formed in series between the MOSFET's source and drain regions under appropriate bias. The gate electrode is separated from the device's active area by an intervening gate insulator, typically silicon dioxide. Because the gate is insulated from the active area, little if any gate current is required in either the on-state or off-state. The gate current is also kept small during switching because the gate forms a capacitor with the device's active area. Thus, only charging and discharging current ("displacement current") is required. The high input impedance of the gate, caused by the presence of the gate insulator, is a primary feature of the power MOSFET. Moreover, because of the minimal current demands on the gate, the gate drive circuitry can be easily implemented on a single chip. As compared to bipolar technology, the simple gate control typically provides for a large reduction in cost and a significant improvement in reliability.
These benefits may be offset, to some extent, by the typically high on-state resistance of the MOSFET's active region, which arises from the absence of minority carrier injection. This on-state resistance is typically a function of the device's channel resistance, JFET neck resistance and drift region (e.g., epitaxial layer) resistance. As a result, a power MOSFET's operating forward current density may be limited to relatively low values, typically in the range of 10 A/cm.sup.2, for a 600 V device, as compared to 40-50 A/cm.sup.2 for the bipolar transistor. Notwithstanding this recognized tradeoff in device characteristics, state-of-the-art low voltage power MOSFETs are still expected to simultaneously have extremely low on-state resistance, low power dissipation and high forward blocking voltage capability (e.g., breakdown voltage). Moreover, because power MOSFETs are frequently used in applications which utilize inductive loads, they are also required to have high unclamped inductive switching (UIS) capability (i.e., high "ruggedness").
Simultaneously satisfying each of these requirements, however, has been an illusive goal since each requirement is typically inversely related to at least one other requirement. For example, conventional techniques to increase the blocking voltage capability of a power MOSFET may result in an increase in on-state resistance and techniques to reduce on-state resistance may result in a reduction in UIS capability. The tradeoff associated with these device characteristics may become especially critical when designing MOSFETs to operate at very low control voltages. For example, in conventional DMOS-based power MOSFETs, the contributions of the channel region, the JFET neck region and drift region to the on-state resistance may become comparable. However, because the resistivity and thickness of the drift region are normally predetermined based on a desired forward blocking voltage, most attention has been directed towards reducing channel and JFET neck resistance.
As will be understood by those skilled in the art, the JFET neck resistance can be reduced by using high dose JFET implants and/or wider neck regions, however, these modifications may result in lower breakdown voltage. These modifications may also push the location of breakdown towards the substrate-gate insulator interface (extending opposite the gate electrode) and thereby lower device reliability and UIS capability. As another alternative, the channel resistance can be reduced by establishing higher channel densities during on-state conduction, using shorter channel lengths and lower body region doping concentrations, and using thinner gate oxides. However, the use of short channel lengths may increase parasitic short-channel effects and the use of lower body region doping concentrations may degrade UIS capability because of the higher lateral body region resistance.
Nonetheless, recent attempts have been made to develop high power MOSFETs with low on-state resistance, high breakdown voltage capability and high UIS capability. One such attempt is disclosed in U.S. Pat. No. 5,338,961 to Lidow et al. In particular, the '961 patent discloses a vertical power MOSFET at FIG. 2 which utilizes a relatively highly doped region 40 (shown as N+) on a more lightly doped drift/epitaxial region (shown as N-) to reduce on-state resistance. As illustrated by FIG. 2 of the '961 patent, this relatively highly doped region 40 is formed in the JFET neck region of the MOSFET, between two adjacent body regions 30 and 31 (shown as P+). The breakdown voltage of the MOSFET at FIG. 2 is also described as being increased by the presence of relatively deep body region diffusions (shown as P+) having large radius. Here, the portions of the body regions 30 and 31 which have the greatest depth "X", relative to a face on which a gate electrode 24 is formed, are located opposite ends of respective source regions 32 and 33 which do not contribute to forward conduction through respective channel regions 34 and 35. In other words, the deep portions of the body regions 30 and 31 are spaced away from the central JFET neck region which is located within the relatively highly doped region 40.
Techniques to improve the safe operating area (SOA) of power devices by making them less susceptible to destructive voltage breakdown have also included the use of clamping regions with spherical cross-sections. For example, U.S. Pat. No. 5,135,349 to Yilmaz et al. discloses the use of a clamping region 40 (shown as P+) which extends between adjacent unit cells of a power MOSFET (see, FIG. 3B of the '349 patent) or between adjacent unit cells of an insulated-gate bipolar junction transistor (IGBT) (see, FIG. 3A of the '349 patent). As will be understood by those skilled in the art, an IGBT is a hybrid device which combines bipolar conduction characteristics with MOS-controlled current flow. Here, the clamping region 40 is designed to have a lower breakdown voltage than the adjacent unit cells. The preferred unit cells of FIGS. 3A-3B of the '349 patent also include highly doped deep body regions 48a and 48b which are flanked by more lightly doped body regions 68a-d. (See, e.g., Col. 4, '349 patent). FIG. 4 of the '349 patent also illustrates an IGBT which utilizes a graded doping profile between the highly doped body regions 90a and 90b (in wells 96a and 96b) and the drift region 94, to obtain higher breakdown voltage capability. U.S. Pat. No. 5,057,884 to Suzuki et al. also discloses shallow and deep base/body regions formed in "flat bottom" well regions to reduce parasitic transistor turn-on in a power MOSFET (or parasitic thyristor latch-up in an IGBT). U.S. Pat. Nos. 5,034,336 to Seki, 5,160,985 to Akiyama, 5,326,993 to Iwamuro, and 5,702,961 to Park also disclose power semiconductor devices (e.g., MOSFETs, IGBTs) having deep body region extensions that are flanked by shallower portions of the body region.
However, these attempts may provide only limited success in meeting the above-described design tradeoff in a preferred manner. In particular, although the deep body region extensions of the above described devices may reduce body region resistance and improve UIS capability without significantly increasing on-state resistance or significantly decreasing device breakdown voltage, the location of device breakdown will still likely be within the JFET neck region. This means the transient avalanche current during UIS may still flow laterally across the entire body region (underneath the source region) to reach the body/source contact. As will be understood by those skilled in the art, high levels of such lateral current can turn on a parasitic bipolar junction transistor formed by the drift region, body region and source region and, in the case of an IGBT, induce sustained parasitic thyristor latch-up. The current flow lines associated with this avalanche current are best illustrated by FIG. 1 which is a cross-sectional view of a conventional planar DMOS device containing a drift/epitaxial region 2, body region 3, source region 4, insulated gate electrode 5 and source/body contact 6. The use of highly doped deep body region extensions may also lead to an increased threshold voltage (by increasing the majority carrier dopant concentration in the channel region) and a narrower neck region, and both of these consequences may result in higher on-state resistance, especially when the power MOSFET is used in low voltage applications.
Thus, notwithstanding the above-described attempts to develop higher performance power semiconductor devices which more ideally meet all design tradeoffs, there continues to be a need for improved methods of forming power semiconductor devices and devices formed thereby.